1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to a semiconductor memory device in which low level potential of sense amplifiers, memory cells and bit lines constituting a memory cell array is adapted to be higher than the low level of the word lines of the chip body, in a dynamic random access memory including a memory cell array arranged on a semiconductor substrate, sense amplifiers and circuitry for controlling these.
2. Description of the Background Art
FIG. 101 is a schematic diagram showing a main portion of a conventional DRAM. Referring to FIG. 101, a memory cell MC is connected to a word line WL and a bit line pair BL, BL. Bit line pair BL and BL is connected to an n channel sense amplifier 2, an equalizer circuit 3 and a p channel sense amplifier 4 through transfer gates Tr71 and Tr72. Transfer gates Tr71 and Tr72 are controlled by a gate control signal BLI. To equalizer circuit 3, a VBL signal at the potential of 1/2Vcc as well as an EQ signal are applied. In response to the EQ signal, equalizer circuit 3 precharges bit lines BL and BL to 1/2 Vcc by VBL signal. Sense amplifiers 2 and 4 are to amplify a small potential difference read from the memory cell MC to the bit line pair BL and BL. Sense amplifier 2 is activated when a sense amplifier activating signal SO is applied to a sense drive line SN, while sense amplifier 4 is activated when an activating signal SO is applied to a sense drive line SP.
FIG. 102 is a time chart showing the operation of the memory array shown in FIG. 101. There are a plurality of blocks of the memory array shown in FIG. 101, and each block is activated when a corresponding block activating signal is applied thereto. However, at this time, sense amplifiers 2 and 4 have not yet been activated. When data is to be read from memory cell MC, the BLI signal attains to the "H" level, transfer gates TR71 and TR72 are rendered conductive, and bit line pair BL, BL is connected to sense amplifiers 2 and 4 and to equalizer circuit 3. When word line WL rises to the boosted voltage Vpp as shown in (a) of FIG. 102, a small potential difference is read from memory cell MC to bit line pair BL and BL, activating signal SO attains to the "H" level and activating signal SO attains to the "L" level as shown in (b) and (c) of FIG. 102, and sense amplifiers 2 and 4 are activated, respectively. The small potential difference between the bit line pair BL and BL is amplified by sense amplifiers 2 and 4, and the potential is enhanced to the level of "H" or "L".
Now, the "L" level of the amplitude of the bit line pair BL and BL is the low level of the word lines. In this case, the "L" level of a non-selected word line is equivalent to the "L" level of the amplitude of the bit line pair BL and BL. Therefore, because of sub threshold leak current of the word line which is at the low level of the word lines, charges stored in the memory cell MC flows to the bit line and the amount of charges decrease, resulting in possible destruction of the data in the memory cell MC. In order to prevent this phenomenon, conventionally, a negative voltage bias Vbb is applied to the memory array portion. However, it requires a negative potential generating circuit for generating the negative voltage bias Vbb. In addition, this approach has disadvantage such as increase of array noise as the current incidental to memory array operation flows to the side of the ground, floating of the "L" level of the non-selected word line, increase of the sub threshold leak current of the word line and degradation of the refresh characteristics.